This invention relates generally to semiconductor devices, and more particularly relates to method and apparatuses for interfacing semiconductor devices with external circuitry.
The field of semiconductor memory devices generally and complementary metal-oxide semiconductor (CMOS) devices in particular is enormously active and rapidly developing. Various categories and sub-categories of semiconductor devices are known and commercially available. The ever-increasing popularity and ubiquity of computers and computer-based devices, both in the consumer and industrial realms, is such that the demand for semiconductor memory devices of a variety of different types will continue to grow for the foreseeable future.
Semiconductor devices require input, output, and/or input/out (I/O) circuitry for interfacing them with external circuitry, including other semiconductor devices. In the context of a circuit for outputting signals from a semiconductor devices, the term xe2x80x9coutput driverxe2x80x9d is often used. For example, on the input/output terminals of a semiconductor memory device, an output (or input/output) driver is required to present binary digital output signals on the I/O terminals. Most commonly, a logical low (binary xe2x80x9c0xe2x80x9d) signal is represented in a semiconductor by a substantially zero voltage. As semiconductor technologies have evolved, the standard voltage for representing a logical xe2x80x9chighxe2x80x9d (binary xe2x80x9c1) signal has been being reduced from an earlier standard of 5 volts to an increasingly common 3.3 volts. For reasons relating to, among other factors, power consumption, thermal performance, speed, and device size, it is entirely possible that the standard voltage for representation of a logical high (binary xe2x80x9c1xe2x80x9d) voltage could be reduced even further as semiconductor technologies evolve.
The shift to lower operating voltages in semiconductor devices has not occurred all at once within the semiconductor industry. Hence, there has been an ongoing desire for semiconductor devices which are capable of recognizing a range of logical voltages, for example, recognizing either 1.8 volts or 2.5 volts as a logical high (binary xe2x80x9c1xe2x80x9d) voltage. Even for semiconductor devices intended to operate only at one operating voltage, however, care must be taken to ensure that the device can withstand an occasional or even sustained overdrive condition without adverse consequences. Those of ordinary skill in the art will understand that the term xe2x80x9coverdrive conditionxe2x80x9d is used to refer to voltages or currents at an electrical node, such as at an input pad, which exceed specified levels, such as a manufacturer""s specification of the xe2x80x9cnormalxe2x80x9d operating parameters of a part. xe2x80x9cOverdrive conditionsxe2x80x9d can be contrasted with what is typically referred to as a xe2x80x9cnormal operating conditionsxe2x80x9d, i.e., condition specified by a semiconductor device manufacturer to be within specified limits. By way of example, for an input/output pin on a semiconductor device specified for operation with a supply voltage of 3.3 volts, a voltage of greater than five volts present on that pad might be considered an overdrive condition.
Those of ordinary skill in the art will be familiar with some of the widely recognized and well-documented problems associated with overdrive conditions occurring at I/O terminals (and other electrical nodes) of semiconductor devices. One especially common problem is the potential for latch-up conditions resulting from overdrive conditions within a semiconductor device. Those of ordinary skill in the art will understand that a common type of xe2x80x9clatch-upxe2x80x9d condition is caused when parasitic (i.e., unintentional) conduction paths are created between otherwise separate semiconductor regions as a result of an overdriving of the I/O pad. Such conditions can create sustained current flow between adjacent semiconductor regions, causing the semiconductor circuitry to cease proper function or even to self-destruct.
Semiconductor I/O devices are especially susceptible to latch-up owing to their exposure to external conditions, including the application of external voltages or currents exceeding specified limits. A semiconductor input/output circuit commonly comprises a xe2x80x9cpull-upxe2x80x9d device and a xe2x80x9cpull-downxe2x80x9d device. The term xe2x80x9cpull-upxe2x80x9d device refers to the circuitry adapted to pull an output node to the desired logical high (binary xe2x80x9c1xe2x80x9d) voltage, e.g., 3.3 volts or 5 volts, whereas the term xe2x80x9cpull-downxe2x80x9d device refers to the circuitry adapted to pull an output node to a desired logical low (binary xe2x80x9c0xe2x80x9d) voltage (typically 0 voltages). In order to satisfy the performance requirements of modern semiconductor circuits, conventional data output buffers often employ N-channel metal oxide semiconductor (NMOS) transistors in both the pull-up and pull-down circuits. Perceived advantages of using NMOS pull-up transistors in an output driver rather than P-channel metal oxide semiconductor (PMOS) transistors include smaller size, and less susceptibility to latch-up. These considerations are discussed in U.S. Pat. No. 6,141,263 to Protzman, entitled xe2x80x9cCircuit and Method for a High Transfer Rate Output Driver,xe2x80x9d which patent is commonly assigned to the assignee of the present invention and is hereby incorporated by reference herein in its entirety.
On the other hand, there are also perceived advantages to using PMOS transistors in output drivers. One such advantage is switching speed, since it is generally understood that a PMOS pull-up transistor switches at a faster speed than an NMOS transistor, not requiring a boosted control signal on its gate. However, unlike an NMOS driver, a PMOS driver has the potential to increase a buffer circuit""s susceptibility to cause latch-up of adjacent CMOS circuits. In common implementations of PMOS output drivers, when the I/O pad""s voltage or current conditions exceed certain levels, a parasitic P+to N-well junction is forward-biased, and a parasitic P-N diode can be formed between the pad""s P+ diffusion and the N+ diffusion guard ring. This results in heavy injected current into the N-well. This injected current is then capable of forward biasing other parasitic PNP structures, ultimately leading to the injection of hole current into the P substrate.
In a so-called xe2x80x9cpumped substratexe2x80x9d design, where the substrate is not directly tied to ground but instead is negatively biased by a P-substrate charge pump, any large injection of hole current into the substrate can readily overwhelm the pump, making such a design highly susceptible to I/O-injected latch-up. The latch-up problem is potentially more severe in pumped substrate devices, because the typical latch-up prevention scheme of grounding the P-substrate with P+ guard rings cannot be utilized. The negative pump generator can only provide a limited amount of negative current to counter the positive current injected into the P-substrate or P-well. Latch-up occurs when the parasitic PN diode formed by the P-channel driver transistor and the Vcc N+ guard ring biases the N-well to a high enough voltage to turn on the parasitic vertical PNP transistor connected between the P+ driver diffusion, the N-well, and the P-substrate. If enough hole current is injected into the P-substrate, then the local P-substrate voltage potential can increase to above Vdiode (the forward voltage of a PN diode). This increase in the P-substrate potential will forward-bias parasitic PN diodes of nearby Vss N+ active areas, resulting in the triggering of the parasitic PNPN latch-up devices between I/O and Vss or between the power supplies Vcc and Vss.
Although there are many aspects of circuit design and layout that are important to the subject of latch-up, there are a few well-known basic features that can be incorporated into a CMOS device to reduce susceptibility to latch-up. Among the more important of these are design techniques that avoid the formation of parasitic bipolar transistors in CMOS circuitry.
For example, one technique that both decouples parasitic bipolar transistors and other parasitic structures to improve isolation of MOS transistors is to form a deep trench between structures on the substrate. Such xe2x80x9ctrench isolationxe2x80x9d typically involves etching a narrow, deep groove in the silicon substrate and then filling the trench with oxide or polysilicon. Such a trench structure, though reasonably effective inxe2x80x94delaying the onset of triggering of latch-upxe2x80x94, undesirably occupies valuable silicon area and complicates the semiconductor fabrication process.
It is also recognized that substrate tie-downsxe2x80x94the regions formed to make ohmic contact with supply voltages for biasing portions of the substrate to desired voltagesxe2x80x94can be configured to diminish parasitic effects. One approach in particular is to configure such substrate tie-downs as rings which encircle certain regions thereby functioning as guard rings which reduce the lifetime of minority carriers (electrons in a P-well, holes in an N-well). An N-well formed in a P-substrate, for example, may have a well tie-down coupled to the supply potential and configured as a ring around its perimeter, so as to act as a sink for minority carriers injected into the N-well when neighboring parasitic devices are forward-biased. This approach is discussed in U.S. Pat. No. 5,801,423 to Manning et al., entitled xe2x80x9cApparatus for Improving Latchup Immunity in a Dual Polysilicon Gate Process,xe2x80x9d which patent is hereby incorporated herein by reference in its entirety.
The use of tie-downs or guard rings alone may not sufficiently delay the onset of latch-up in a given implementation. Indeed, as discussed herein below, guard rings themselves can be contributing factors to the formation of parasitic structures, since those guard rings that are tied to a supply voltage can serve as the source of parasitic current.
Thus, despite semiconductor designers"" ongoing efforts to minimize I/O circuitry""s tolerance of overdrive conditions, there continues to be an ongoing need for I/O buffer/driver circuitry that is more tolerant of overdrive conditions and less susceptible to latch-up.
In view of the foregoing considerations, the present invention is directed to an output driver circuit for a semiconductor device.
In one embodiment of the invention, a control transistor is provided for the selective decoupling of a particular connection within the driver circuit to a supply potential. An overdrive detection circuit coupled to the output node of the device is adapted to detect overdrive conditions on the output node, including the application of excessive voltages and the injection of current, and upon detection of such overdrive conditions, to assert a control signal that is applied to the control transistor""s gate. In operation, the overdrive detection circuit functions to disable the control transistor, thereby decoupling the connection to the supply potential and averting conditions leading to undesirable parasitic conduction within the CMOS circuit.
In accordance with one feature of the invention, the overdrive detection circuit is conditioned to respond only to overdrive conditions on an output node, and absent such overdrive conditionsxe2x80x94such as during normal pull-up operations where voltage and/or current conditions are maintained within acceptable specified limitsxe2x80x94to maintain connection of the supply potential to the driver circuit.
In accordance with another feature of the invention, the overdrive detection circuit does not itself require additional control circuitry likely to adversely affect the operational performance of the driver circuit. Additionally, the present invention does not involve the use of a decoupling switch tied directly to the output node, thereby altering the operational properties of the driver circuit.